1. Field of the Invention
The present invention is related to the field of integrated circuit memories and, in particular, to memory designs made on custom chips and, more specifically, on gate arrays or master slices.
2. Description of the Prior Art
It is well-known in the art to preprocess an integrated circuit up to its final stages of layout and to leave the last processing or fabrication steps for later differentiation by use of fuse links or metalization patterns. This is known as a semicustom chip which has come to provide an option falling between the high volume low cost standard logic chips and expensive handcrafted custom integrated circuits. There are basicallly three forms of semicustom logic chips presently used: (1) field programmable integrated circuits such as programmable array logic chips and field programmable logic arrays; (2) gate arrays or master slices; and (3) standard cell or polycell designs.
Often, with such semicustom chips, it becomes necessary to devote all or part of the available chip space to a memory. Often, such a memory will be totally isolated, i.e., will have no inputs or outputs which will be directly coupled to any of the chip pins.
Therefore, it becomes necessary in using semicustom chips to be able to design such internal memories in a manner not only which is consistent with the architecture of the remaining on-chip circuitry but which is capable of operating with some measure of reliability notwithstanding its electric inaccessibility to any circuit off the chip. Moreover, what is needed is a chip which is fabricated in such a manner that connections between circuit groups on the chip can be efficiently made, thereby maximizing both the ease and density by which complex circuits, including memories can utilize the available chip space.
At present, there is a reluctance to use semicustom chips for memories inasmuch as even the semicustom design of the memory is highly dependent upon the word length assumed within the architecture of the memory. Furthermore, semicustom chips often do not readily lend themselves to highly efficient use in complex circuits which may incorporate one or more internal memories. The preprocessed gates and the metalizations required to interconnect the gates often are not optimally situated on the chip for a highly efficient utilization in such complex circuits. Moreover, when memories are used in such complex circuits in semicustom chips and are necessarily isolated on the chip, no simple design or protocol has heretofore existed to allow the reliability of the memory to be determined when there is no input or output to the memory from the chip pins.
The present invention as described below and shown in the figures overcomes each of these shortcomings of the prior art.